Intel’s processor Generation Arrow Lake Alias Core Ultra 200 is still not fully on the market, as the first and detailed information about successor Panther Lake is circulating. Panther Lake must appear before the end of the year – following the new name scheme as the core ultra 300 – and for the first time, the brand that runs the assembly line in the brand new production process. The latter Intel hopes that the market leader TSMC is expected to find a connection in manufacturing technology again. In Arrow Lake, TSMC produces all chip locations except interpreting, which connects individual parts.
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In Panther Lake, not only the production of CPU chiplets should be transferred to its own arms: according to a data sheet, Licker Jaihan has published, Intel will also be the CPU core (performance, performance, performance, number and compilation . The expansion phase H after the meteor lake (Core Ultra 100 H: 6P core, 8 E-Nuclis, 2 LP-E core) and derived and fell down and fell down and fell down and (Core Ultra 100u: 2p Corps, 8 E. Guth, 2 LP-E core). Despite the new microoricatecture for the respective nuclei, they were taken for the core Ultra 200H or Core Ultra 200U. The core Ultra with 8 P and 16 E-Nukelai was newly added to the top of Ultra 200HX, but without LP-E core.
Sarden measures
For the Panther Lake, as H levels according to Jaikin, there are only 4 P-Plus 8 E kernels, so a third low P core. Since there is hardly any scope with a low number of P cores to change the compilation for small U-level, according to Jaikin, they should be diluted to any other location: they should no longer get an e-needle. The published material cannot be seen whether there will still be LP-E core which prevent deletion. However, our intestine is not a sense of intestine, however, because LP-E Kernels neither play a role in the HX model on top nor especially with Lunar Lake (Core Ultra 200V) for mobile notebooks.
It is also not clear what it means in the context of the expected computing power. According to Jaykihn, Intel turns on another set screw: Nominal waste heat (PL1) should remain as before, but PL2 increases from 55 to 64 watts. PL2 is the value that CPUS can burn in its turbo frequencies until the cooling systems of the notebook still stores and do not cross the limit of other parameters such as permissible maximum current. The slim-down U level 15 watt should remain as nominal on PL1.
Similarly, it is not yet known that Panther Lake Hypertharading will celebrate their return, which replaces a real two virtual seeds. In the meteorite lake, P-Kern still dominates the technology, but Intel has closed the ceremony at Arrow Lake.
Tick-talk, but different
And then it is an open question as to which market segments Panther Lake is planned. The meteor lake is clearly focused on the notebook. On the other hand, the desktop-PCS had to wait for the Intel CPU to the Arrow Lake to be made of chiplets, while you would have to search for mobile-specific innovations with a magnifying glass. For notebooks, Nard Chandra Lake came to meditation instead, which was fully developed outside the main chain.
Prototype Notebook with Panther Lake
(Image: C’T/MUE)
Panther Lake has to mention the benefits of the Lunar lake including an integrated graphics unit, which is for the Copilot+ Sangat NPU and a powerful integrated graphics unit, as written above, if possible, produced in its fabs of Intel if possible With Panther Lake (4P+8E) should be cleaned against the lunar lake (4p+4e). And who knows that Intel’s engineers are still in the store because they have clearly committed themselves at chip locations: if you add about two CPU chips of 4P+8E, phase.
In any case, there should be something that should come up with Nova Lake, the successor of the Panther Lake, which will eventually become the core Ultra 400: Rumor Chefs Talk to 48 CPU Core (16P+32E), which 8P+++ The two chipplates are dealt with. 16e became. But this is something for powerful desktop PC; With the notebook, 8P+16E should remain maximum. Nova Lake is not talking about LP-E core, but again as the smallest U level of 4P core without e-core support.
(MUE)
